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Motorola DSP56303

The DSP56303 is a 24-bit processor: each memory location refers to a 24-bit word. The processor has three address spaces, each accessed using a 24-bit address (16 Mword):

• P memory, containing the program code.
• X memory, containing data.
• Y memory, containing data.

• L memory is the combination of X and Y memory: each read/write accesses 48 bits.

Processor registers

The processor treats 24-bit (or 48-bit) values as two's complement fractional values, with a fixed binary point to the left of the word; values are in the range –1 <= n < 1:

800000 = –1.0
C00000 = –0.5
000000 = 0.0
000001 = +0.000000119 (2^–23)
400000 = +0.5
7FFFFF = +0.999999

Data ALU input registers:

X (48 bits) X1 (24 bits)   X0 (24 bits)

Y (48 bits) Y1 (24 bits)   Y0 (24 bits)

Data ALU accumulator registers:

A (56 bits)   A2 (8 bits)  A1 (24 bits)   A0 (24 bits)

B (56 bits)   B2 (8 bits)  B1 (24 bits)   B0 (24 bits)

Address registers:

Address:		Offset:		Modifier:
R0 (24 bits)  | R7 (24 bits)		N0 (24 bits)  | N7 (24 bits)		M0 (24 bits)  | M7 (24 bits)

These registers can be used as general purpose registers, or for indirect addressing (memory pointers):

(Rn)		read/write (Rn)
(Rn)+		read/write (Rn); Rn := Rn+1 modulo Mn+1
(Rn)–		read/write (Rn); Rn := Rn–1 modulo Mn+1
(Rn)+Nn		read/write (Rn); Rn := Rn+Nn modulo Mn+1
(Rn)–Nn		read/write (Rn); Rn := Rn–Nn modulo Mn+1
(Rn+Nn)		read/write (Rn+Nn modulo Mn+1)
–(Rn)		Rn := Rn–1 modulo Mn+1; read/write (Rn)
(Rn+nnn)		read/write (Rn+nnn modulo Mn+1)

Machine code

Each processor instruction occupies one 24-bit word, with an optional (instruction dependent) second 24-bit word containing immediate data, an address, etc. The op-code for many instructions only occupies the lower 8 bits: these are called parallel instructions, as the upper 16 bits of the instruction word may contain the op-code for a data move operation, which is performed in parallel.

Parallel instructions (op-code only occupies the lower 8 bits of the 24-bit word):

ABS		A/B
ADC		X/Y, A/B
ADD		B/A/X/Y/Xn/Yn, A/B
ADDL		B/A, A/B
ADDR		B/A, A/B
AND		Xn/Yn, A/B
ASL		A/B
ASR		A/B
CLR		A/B
CMP		B/A/Xn/Yn, A/B
CMPM		B/A/Xn/Yn, A/B
EOR		Xn/Yn, A/B
LSL		A/B
LSR		A/B
MAC		±Xn/Yn, Xn/Yn, A/B
MACR		±Xn/Yn, Xn/Yn, A/B
MAX		A, B
MAXM		A, B
MPY		±Xn/Yn, Xn/Yn, A/B
MPYR		±Xn/Yn, Xn/Yn, A/B
NEG		A/B
NOT		A/B
OR		Xn/Yn, A/B
RND		A/B
ROL		A/B
ROR		A/B
SBC		X/Y, A/B
SUB		B/A/X/Y/Xn/Yn, A/B
SUBL		B/A, A/B
SUBR		B/A, A/B
TFR		B/A/Xn/Yn, A/B
TST		A/B

Parallel moves (op-code only occupies the upper 16 bits of the 24-bit word):

Short immediate #8bits,	Xn/Yn/An/Bn/A/B/Rn/Nn
Register-to-register Xn/Yn/An/Bn/A/B/Rn/Nn,	Xn/Yn/An/Bn/A/B/Rn/Nn
Address register update (Rn)+ (Rn)– (Rn)+Nn (Rn)–Nn
X/Y memory #24bits, X/Y:6bits, X/Y:24bits, X/Y:–(Rn), X/Y:(Rn+Nn), X/Y:(Rn), X/Y:(Rn)+, X/Y:(Rn)–, X/Y:(Rn)+Nn, X/Y:(Rn)–Nn,	Xn/Yn/An/Bn/A/B/Rn/Nn  Xn/Yn/An/Bn/A/B/Rn/Nn  Xn/Yn/An/Bn/A/B/Rn/Nn  Xn/Yn/An/Bn/A/B/Rn/Nn  Xn/Yn/An/Bn/A/B/Rn/Nn  Xn/Yn/An/Bn/A/B/Rn/Nn  Xn/Yn/An/Bn/A/B/Rn/Nn  Xn/Yn/An/Bn/A/B/Rn/Nn  Xn/Yn/An/Bn/A/B/Rn/Nn  Xn/Yn/An/Bn/A/B/Rn/Nn
Xn/Yn/An/Bn/A/B/Rn/Nn, Xn/Yn/An/Bn/A/B/Rn/Nn, Xn/Yn/An/Bn/A/B/Rn/Nn, Xn/Yn/An/Bn/A/B/Rn/Nn, Xn/Yn/An/Bn/A/B/Rn/Nn, Xn/Yn/An/Bn/A/B/Rn/Nn, Xn/Yn/An/Bn/A/B/Rn/Nn, Xn/Yn/An/Bn/A/B/Rn/Nn, Xn/Yn/An/Bn/A/B/Rn/Nn,	X/Y:6bits  X/Y:24bits  X/Y:–(Rn)  X/Y:(Rn+Nn)  X/Y:(Rn)  X/Y:(Rn)+  X/Y:(Rn)–  X/Y:(Rn)+Nn  X/Y:(Rn)–Nn
L memory L:6bits, L:24bits, L:–(Rn), L:(Rn+Nn), L:(Rn), L:(Rn)+, L:(Rn)–, L:(Rn)+Nn, L:(Rn)–Nn,	X/Y/A/B/A10/B10/AB/BA  X/Y/A/B/A10/B10/AB/BA  X/Y/A/B/A10/B10/AB/BA  X/Y/A/B/A10/B10/AB/BA  X/Y/A/B/A10/B10/AB/BA  X/Y/A/B/A10/B10/AB/BA  X/Y/A/B/A10/B10/AB/BA  X/Y/A/B/A10/B10/AB/BA  X/Y/A/B/A10/B10/AB/BA
X/Y/A/B/A10/B10/AB/BA, X/Y/A/B/A10/B10/AB/BA, X/Y/A/B/A10/B10/AB/BA, X/Y/A/B/A10/B10/AB/BA, X/Y/A/B/A10/B10/AB/BA, X/Y/A/B/A10/B10/AB/BA, X/Y/A/B/A10/B10/AB/BA, X/Y/A/B/A10/B10/AB/BA, X/Y/A/B/A10/B10/AB/BA,	L:6bits  L:24bits  L:–(Rn)  L:(Rn+Nn)  L:(Rn)  L:(Rn)+  L:(Rn)–  L:(Rn)+Nn  L:(Rn)–Nn
X memory and register #24bits, X:24bits, X:–(Rn), X:(Rn+Nn), X:(Rn), X:(Rn)+, X:(Rn)–, X:(Rn)+Nn, X:(Rn)–Nn,	Xn/A/B  Xn/A/B  Xn/A/B  Xn/A/B  Xn/A/B  Xn/A/B  Xn/A/B  Xn/A/B  Xn/A/B		A/B, A/B, A/B, A/B, A/B, A/B, A/B, A/B, A/B,	Yn  Yn  Yn  Yn  Yn  Yn  Yn  Yn  Yn
Xn/A/B, Xn/A/B, Xn/A/B, Xn/A/B, Xn/A/B, Xn/A/B, Xn/A/B, Xn/A/B,	X:24bits  X:–(Rn)  X:(Rn+Nn)  X:(Rn)  X:(Rn)+  X:(Rn)–  X:(Rn)+Nn  X:(Rn)–Nn		A/B, A/B, A/B, A/B, A/B, A/B, A/B, A/B,	Yn  Yn  Yn  Yn  Yn  Yn  Yn  Yn
A/B, A/B, A/B, A/B, A/B, A/B, A/B,	X:–(Rn)  X:(Rn+Nn)  X:(Rn)  X:(Rn)+  X:(Rn)–  X:(Rn)+Nn  X:(Rn)–Nn		X0, X0, X0, X0, X0, X0, X0,	A/B  A/B  A/B  A/B  A/B  A/B  A/B
Register and Y memory A/B, A/B, A/B, A/B, A/B, A/B, A/B, A/B, A/B	Xn  Xn  Xn  Xn  Xn  Xn  Xn  Xn  Xn		#24bits, Y:24bits, Y:–(Rn), Y:(Rn+Nn), Y:(Rn), Y:(Rn)+, Y:(Rn)–, Y:(Rn)+Nn, Y:(Rn)–Nn,	Yn/A/B  Yn/A/B  Yn/A/B  Yn/A/B  Yn/A/B  Yn/A/B  Yn/A/B  Yn/A/B  Yn/A/B
A/B, A/B, A/B, A/B, A/B, A/B, A/B, A/B,	Xn  Xn  Xn  Xn  Xn  Xn  Xn  Xn		Yn/A/B, Yn/A/B, Yn/A/B, Yn/A/B, Yn/A/B, Yn/A/B, Yn/A/B, Yn/A/B,	Y:24bits  Y:–(Rn)  Y:(Rn+Nn)  Y:(Rn)  Y:(Rn)+  Y:(Rn)–  Y:(Rn)+Nn  Y:(Rn)–Nn
Y0, Y0, Y0, Y0, Y0, Y0, Y0,	A/B  A/B  A/B  A/B  A/B  A/B  A/B		A/B, A/B, A/B, A/B, A/B, A/B, A/B,	Y:–(Rn)  Y:(Rn+Nn)  Y:(Rn)  Y:(Rn)+  Y:(Rn)–  Y:(Rn)+Nn  Y:(Rn)–Nn
X and Y memory X:(Rn), X:(Rn)+, X:(Rn)–, X:(Rn)+Nn,	Xn/A/B  Xn/A/B  Xn/A/B  Xn/A/B		Y:(Rn), Y:(Rn)+, Y:(Rn)–, Y:(Rn)+Nn,	Yn/A/B  Yn/A/B  Yn/A/B  Yn/A/B
Xn/A/B, Xn/A/B, Xn/A/B, Xn/A/B,	X:(Rn)  X:(Rn)+  X:(Rn)–  X:(Rn)+Nn		Yn/A/B, Yn/A/B, Yn/A/B, Yn/A/B,	Y:(Rn)  Y:(Rn)+  Y:(Rn)–  Y:(Rn)+Nn

Each processor instruction typically executes in from 1 to 6 clock cycles.

Last updated 20th January 2004, Peter Dziwior.